1. Field of the Invention
The present invention relates, in general, to a method for fabricating a DRAM cell, and more particularly, to a method for increasing the efficient area of a bellows-type storage electrode, thereby increasing the capacitance of a capacitor of a DRAM cell.
2. Description of the Prior Art
As the area which is occupied by a unit cell decreases, the integration degree of a semiconductor device increases. However, the high integration of a semiconductor device requires that a capacitor not be reduced in the capacitance necessary to operate, for example, a DRAM cell and secure at least about 40 femtofared (fF).
Based on such requirements for the high integration of a semiconductor device, various structures of a capacitor have been developed to secure a sufficient capacitance of a unit DRAM cell in such reduced area. For example, three-dimensional structures of a capacitor, such as stack, cylinder, pin and so on, were fabricated.
Of those three-dimensional structures of a capacitor, pin-type capacitors have widely been employed due to their simple fabrication processes. As the cell area is reduced, the number of pins should be increased to maintain the capacitance of the capacitor at a requisite level. A significant disadvantage of the conventional pin-type capacitors is that numerous process steps must be undertaken to increase the number of the pins. That is, many insulation layers and polysilicon layers are repeatedly formed, conducting a large number of CVD processes. In the meanwhile, particles and defects may be more frequently generated, thereby decreasing the production yield.